https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105394
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Assignee|unassigned at gcc dot gnu.org |rguenth at gcc dot
gnu.org
Ever confirmed|0 |1
Last reconfirmed| |2022-04-26
Status|UNCONFIRMED |ASSIGNED
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Hmm, in my cross-arm build I get
> ./cc1plus -quiet t.c -I include -march=armv8.1-m.main+mve -mfloat-abi=hard -O
cc1plus: error: target CPU does not support ARM mode
while in my cross-aarch64 build:
> ./cc1plus -quiet t.c -I include -march=armv8.1-m.main+mve -mfloat-abi=hard -O
cc1plus: error: unrecognized command-line option '-mfloat-abi=hard'
cc1plus: error: unknown value 'armv8.1-m.main+mve' for '-march'
cc1plus: note: valid arguments are: armv8-a armv8.1-a armv8.2-a armv8.3-a
armv8.4-a armv8.5-a armv8.6-a armv8.7-a armv8.8-a armv8-r armv9-a
in the cross-arm build adding -mthumb reproduces the ICE, I guess my
configury (--target=arm-none-linux-gnueabihf --with-float=hard
--with-cpu=cortex-a9 --with-fpu=neon-fp16) plays a role here.
I will have a look.
