[Bug rtl-optimization/94133] GCC loses track of SHIFT optimization

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94133

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
In the first example combine is able to combine:
Trying 13 -> 14:
   13: {r96:SI=r103:SI&0x3f;clobber flags:CC;}
      REG_DEAD r103:SI
      REG_UNUSED flags:CC
   14: {r97:TI=r95:TI<<r96:SI#0;clobber flags:CC;}
      REG_DEAD r96:SI
      REG_DEAD r95:TI
      REG_UNUSED flags:CC
Successfully matched this instruction:
(parallel [
        (set (reg:TI 97)
            (ashift:TI (reg:TI 95 [ *src_10(D) ])
                (subreg:QI (and:SI (reg:SI 103)
                        (const_int 63 [0x3f])) 0)))
        (clobber (reg:CC 17 flags))
    ])
allowing combination of insns 13 and 14
original costs 4 + 32 = 36
replacement cost 36
deferring deletion of insn with uid = 13.
modifying insn i3    14: {r97:TI=r95:TI<<r103:SI&0x3f#0;clobber flags:CC;}
      REG_DEAD r103:SI
      REG_UNUSED flags:CC
      REG_DEAD r95:TI
deferring rescan insn with uid = 14.

BUT in the second example, it is not done as sh % 64 is used twice.

I think there are other examples of this issue in the bug database too.