https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89435
--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r242326. Since that version, we have before ira:
(insn 28 27 36 2 (set (reg:SI 141)
(const_int 255 [0xff])) "pr89435.c":9 182 {*arm_movsi_insn}
(nil))
...
(insn 42 36 43 2 (set (reg:QI 125 [ _18 ])
(subreg:QI (reg:SI 141) 0)) "pr89435.c":9 192 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:SI 141)
(nil)))
...
(insn 78 77 79 6 (set (reg:SI 124 [ _15 ])
(plus:SI (reg:SI 162)
(subreg:SI (reg:QI 125 [ _18 ]) 0))) "pr89435.c":11 4 {*arm_addsi3}
(expr_list:REG_DEAD (reg:QI 125 [ _18 ])
(expr_list:REG_DEAD (reg:SI 162)
(nil))))
and starting with ira:
(insn 42 36 43 2 (set (reg:QI 125 [ _18 ])
(const_int -1 [0xffffffffffffffff])) "pr89435.c":9 192
{*arm_movqi_insn}
(nil))
...
(insn 78 77 79 6 (set (reg:SI 124 [ _15 ])
(plus:SI (reg:SI 162)
(subreg:SI (reg:QI 125 [ _18 ]) 0))) "pr89435.c":11 4 {*arm_addsi3}
(expr_list:REG_DEAD (reg:SI 162)
(expr_list:REG_DEAD (reg:QI 125 [ _18 ])
(nil))))
ARM has:
#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) \
(TARGET_THUMB ? ZERO_EXTEND : \
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
Does that mean that (set (reg:QI 125) (const_int -1)) instruction should
actually set the register to 0xff rather than 0xffffffff?
