https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88952
--- Comment #9 from Christopher Leonard <christopher.leonard at abaco dot com> --- (In reply to Andrew Pinski from comment #6) > Yes the order is always hi:lo (reg:reg+1) on all targets I know of This is definitely not the natural choice (on any platform: I agree, endianness is irrelevant here) so I would recommend documenting this as well, and potentially recommending in the docs to explicitly cast e.g. a parameter for a function-style macro used as an input operand expression for inline asm, (%L0 is no help when the size is unknown, it seems to select the "next" register when you give a 32-bit type, which isn't even loaded with a value in the generated PPC assembly). This is how the code messed up for me, I wrote a macro function to generate MTSPR instructions for a given SPR and load value (this is needed since the SPR number used in MTSPR is immediate, there is not alternative where you can take the SPR from a register). One of the constants I used in the calculation of an SPR's load value became a 64-bit type in a later code change, making the input operand 64-bit instead of 32-bit, breaking my code.
