https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83565
--- Comment #30 from Eric Botcazou <ebotcazou at gcc dot gnu.org> --- As pointed out by Segher in comment #14, the problem ultimately comes from the ambiguity of WORD_REGISTER_OPERATIONS. Quoting him: "WORD_REGISTER_OPERATIONS isn't well-defined. """ @defmac WORD_REGISTER_OPERATIONS Define this macro to 1 if operations between registers with integral mode smaller than a word are always performed on the entire register. Most RISC machines have this property and most CISC machines do not. """ What operations? For some operations it can never be true (rotates, shifts, all slightly more complex operations). For machines that have explicit operations in more than one size it cannot be true, either." I'm leaving out the second case (explicit operations in more than one size) and discussing the first case. It turns out that, in SPARC-V9 (64-bit architecture), the 3 32-bit shift operations (sll, srl, sra) do operate on the entire 64-bit registers with the expected semantics (e.g. srl clears the upper 32 bits and sra fills them with a copy of the sign bit of the lower part) so, on SPARC, you can apply WORD_REGISTER_OPERATIONS to shifts (there is no rotate instruction). So it appears that we have 2 classes of RISC machines, the ones supporting a strong version of WORD_REGISTER_OPERATIONS and the others only a weak one.
