[Bug target/61633] AArch64 SISD ASHR instruction split clobbers input register.

[mshawcroft at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61633

--- Comment #2 from mshawcroft at gcc dot gnu.org ---
Author: mshawcroft
Date: Mon Jun 30 11:58:18 2014
New Revision: 212143

URL: https://gcc.gnu.org/viewcvs?rev=212143&root=gcc&view=rev
Log:
[AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_<mode>3 split.

        Backport from Mainline
        2014-06-30  Marcus Shawcroft  <marcus.shawcr...@arm.com>

        PR target/61633
        * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3):
        Add alternative; make early clobber.  Adjust both split patterns
        to use operand 0 as the working register.


Modified:
    branches/gcc-4_9-branch/gcc/ChangeLog
    branches/gcc-4_9-branch/gcc/config/aarch64/aarch64.md