On Thu, Jul 05, 2018 at 02:58:29PM +0100, Pete French wrote:
> > Which other files ?
> 
> sys/x86/include/specialreg.h and sys/x86/x86/cpu_machdep.c
> 
> Those are in your original patch as well as the change
> to sys/amd64/amd64/initcpu.c, but your email earlier only
> patches sys/amd64/amd64/initcpu.c and not the others.
> 
> So I assumed I would keep the changes to the other two files ?


Right, I forgot about mwait. specialreg.h is cosmetics which I already
committed.

diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index ccc5e64d0c4..bb342f42dec 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -130,6 +130,30 @@ init_amd(void)
                }
        }
 
+       /* Ryzen erratas. */
+       if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 &&
+           (cpu_feature2 & CPUID2_HV) == 0) {
+               /* 1021 */
+               msr = rdmsr(0xc0011029);
+               msr |= 0x2000;
+               wrmsr(0xc0011029, msr);
+
+               /* 1033 */
+               msr = rdmsr(0xc0011020);
+               msr |= 0x10;
+               wrmsr(0xc0011020, msr);
+
+               /* 1049 */
+               msr = rdmsr(0xc0011028);
+               msr |= 0x10;
+               wrmsr(0xc0011028, msr);
+
+               /* 1095 */
+               msr = rdmsr(0xc0011020);
+               msr |= 0x200000000000000;
+               wrmsr(0xc0011020, msr);
+       }
+
        /*
         * Work around a problem on Ryzen that is triggered by executing
         * code near the top of user memory, in our case the signal
diff --git a/sys/x86/x86/cpu_machdep.c b/sys/x86/x86/cpu_machdep.c
index d897d518cbc..3416f949686 100644
--- a/sys/x86/x86/cpu_machdep.c
+++ b/sys/x86/x86/cpu_machdep.c
@@ -709,6 +709,13 @@ cpu_idle_tun(void *unused __unused)
 
        if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
                cpu_idle_selector(tunvar);
+       else if (cpu_vendor_id == CPU_VENDOR_AMD &&
+           CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
+               /* Ryzen erratas 1057, 1109. */
+               cpu_idle_selector("hlt");
+               idle_mwait = 0;
+       }
+
        if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
                /*
                 * Apollo Lake errata APL31 (public errata APL30).
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