On Sat, Mar 07, 2009 at 05:17:57PM +0000, ian j hart wrote:
> On Tuesday 20 January 2009 02:45:19 Pyun YongHyeon wrote:
> > On Mon, Jan 19, 2009 at 06:33:46PM -0500, Jung-uk Kim wrote:
> > > On Monday 19 January 2009 04:33 pm, Jung-uk Kim wrote:
> > > > I found something interesting. I have another RTL8169SC that works
> > > > perfectly fine without the patch. The hardware revision is
> > > > 0x18000000. After reading Linux driver (drivers/net/r8169c), I
> > > > realised they use different masks for hardware revisions. With
> > > > their logic, non-working chip seems to be 0x98000000 (8110SCe)
> > > > while working chip seems to be 0x18000000 (8110SCd) with
> > > > 0xfc800000. FYI...
> > >
> > > Now armed with the information, I made it work without reverting
> > > memory mapped I/O. :-)
> > >
> > > http://people.freebsd.org/~jkim/re/re.current2.diff
> > > http://people.freebsd.org/~jkim/re/re.stable2.diff
> >
> > I like the patch. Since only RTL8169 family uses mask 0xfc800000
> > it would be even better we can limit checking scope for RTL8169SC
> > by comparing PCI device id. I don't know what other side effect
> > would happen if the mask 0xfc800000 would be used on 8101/8168
> > controllers.
> > If the patch works on RTL8169SC would you commit the patch?
> > I'd like to see multiple commits separated by each enhancements
> > as the patch contains several fixes which are not directly related
> > with the issue.
>
> Where are we on this?
>
> I have a headless firewall box which is not happy with 7.1-RELEASE. I've
> upgraded to 7.1-STABLE as of yesterday and now I'm getting 'PHY read failed'
> errors, although the network did come up, which was an improvement.
>
> Is there a patch I can try?
>
> http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=174&proname=AD3RTLAN-G
>
> re0: <RealTek 8169SC/8110SC Single-chip Gigabit Ethernet> port 0xf200-0xf2ff
> mem 0xfdfff000-0xfdfff0ff irq 18 at device 9.0 on pci0
> re0: Chip rev. 0x18000000
> re0: MAC rev. 0x00000000
> re0: Ethernet address: 00:30:18:ae:1a:1b
> re0: [FILTER]
> re1: <RealTek 8169SC/8110SC Single-chip Gigabit Ethernet> port 0xf000-0xf0ff
> mem 0xfdffd000-0xfdffd0ff irq 19 at device 11.0 on pci0
> re1: Chip rev. 0x18000000
> re1: MAC rev. 0x00000000
> re1: Ethernet address: 00:30:18:ae:1a:1c
> re1: [FILTER]
> re2: <RealTek 8169SC/8110SC Single-chip Gigabit Ethernet> port 0xec00-0xecff
> mem 0xfdffc000-0xfdffc0ff irq 16 at device 12.0 on pci0
> re2: Chip rev. 0x18000000
> re2: MAC rev. 0x00000000
> re2: Ethernet address: 00:30:18:ae:1a:1d
> re2: [FILTER]
>
> r...@pci0:0:9:0: class=0x020000 card=0x10ec16f3 chip=0x816710ec rev=0x10
> hdr=0x00
> r...@pci0:0:11:0: class=0x020000 card=0x10ec16f3 chip=0x816710ec
> rev=0x10 hdr=0x00
> r...@pci0:0:12:0: class=0x020000 card=0x10ec16f3 chip=0x816710ec
> rev=0x10 hdr=0x00
>
Have you tried re(4) in HEAD?
I had one report that re(4) in HEAD still does not fix the issue so
I posted a possible workaround for that. Unfortunately he didn't
report back so I don't know whether it was right workaround or not.
If re(4) in HEAD does not fix the issue, would you try attached
patch and let me know how it goes?
Index: sys/dev/re/if_re.c
===================================================================
--- sys/dev/re/if_re.c (revision 187352)
+++ sys/dev/re/if_re.c (working copy)
@@ -158,6 +158,8 @@
/* Tunables. */
static int msi_disable = 1;
TUNABLE_INT("hw.re.msi_disable", &msi_disable);
+static int prefer_iomap = 0;
+TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
@@ -1131,26 +1133,36 @@
pci_enable_busmaster(dev);
devid = pci_get_device(dev);
- /* Prefer memory space register mapping over IO space. */
- sc->rl_res_id = PCIR_BAR(1);
- sc->rl_res_type = SYS_RES_MEMORY;
- /* RTL8168/8101E seems to use different BARs. */
- if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
- sc->rl_res_id = PCIR_BAR(2);
+ /*
+ * Prefer memory space register mapping over IO space.
+ * Because RTL8169SC does not seem to work when memory mapping
+ * is used always activate io mapping.
+ */
+ if (devid == RT_DEVICEID_8169SC)
+ prefer_iomap = 1;
+ if (prefer_iomap == 0) {
+ sc->rl_res_id = PCIR_BAR(1);
+ sc->rl_res_type = SYS_RES_MEMORY;
+ /* RTL8168/8101E seems to use different BARs. */
+ if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
+ sc->rl_res_id = PCIR_BAR(2);
+ } else {
+ sc->rl_res_id = PCIR_BAR(0);
+ sc->rl_res_type = SYS_RES_IOPORT;
+ }
sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
&sc->rl_res_id, RF_ACTIVE);
-
- if (sc->rl_res == NULL) {
+ if (sc->rl_res == NULL && prefer_iomap == 0) {
sc->rl_res_id = PCIR_BAR(0);
sc->rl_res_type = SYS_RES_IOPORT;
sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
&sc->rl_res_id, RF_ACTIVE);
- if (sc->rl_res == NULL) {
- device_printf(dev, "couldn't map ports/memory\n");
- error = ENXIO;
- goto fail;
- }
}
+ if (sc->rl_res == NULL) {
+ device_printf(dev, "couldn't map ports/memory\n");
+ error = ENXIO;
+ goto fail;
+ }
sc->rl_btag = rman_get_bustag(sc->rl_res);
sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
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