On Thu, Mar 15, 2001 at 05:20:58AM -0800, Peter Wemm wrote:
> > fxp0: <Intel Pro 10/100B/100+ Ethernet> port 0xff20-0xff3f mem 0xff800000-0xf
> f8fffff,0xffbde000-0xffbdefff irq 2 at device 6.0 on pci0
> > fxp0: using memory space register mapping
> > fxp0: Ethernet address 00:a0:c9:49:aa:d3
> > fxp0: PCI IDs: 8086 1229 0000 0000
> > nsphy0: <DP83840 10/100 media interface> on miibus0
> > nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
> > bpf: fxp0 attached
> >
> > This actually does have the NatSemi phy on it and it is correctly detected.
> > Unfortunately, I just locked that machine up with SMPng. oops. I can't
> > verify that it works just yet.. We have another old machine with a NS
> > phy on it (pII based instead of PPro based) and are working on it now.
>
> It appears that the nsphy version is unable to actually transmit packets.
> It is recieving OK, just not sending. (or, the other machines are unable
> to see it, maybe the switch is dropping the packets as "damaged" or
> something?)
Try this following patch to mii/nsphy.c. It appears that we need to
toggle some undocumented bits in order to get this PHY to work with
the fxp driver.
--
Jonathan
Index: nsphy.c
===================================================================
RCS file: /ncvs/src/sys/dev/mii/nsphy.c,v
retrieving revision 1.7
diff -u -r1.7 nsphy.c
--- nsphy.c 2001/02/07 19:57:16 1.7
+++ nsphy.c 2001/03/15 17:14:51
@@ -264,17 +264,20 @@
*/
reg |= PCR_FLINK100;
-#if 0
/*
* Mystery bits which are supposedly `reserved',
* but we seem to need to set them when the PHY
- * is connected to some interfaces!
+ * is connected to some interfaces:
+ *
+ * 0x0400 is needed for fxp
+ * (Intel EtherExpress Pro 10+/100B, 82557 chip)
+ * (nsphy with a DP83840 chip)
+ * 0x0100 may be needed for some other card
*/
reg |= 0x0100 | 0x0400;
-#endif
-/*
+
PHY_WRITE(sc, MII_NSPHY_PCR, reg);
-*/
+
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
/*
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