* Luigi Rizzo <[EMAIL PROTECTED]> [011024 14:03] wrote:
> Well, the question is rather simple... i am running some experiments
> on system with severe load on the PCI bus (basically a router with 4 interfaces
> trying to forward 2..4 streams of 64-byte packets at 100Mbit/s (i.e. 144kpps
> on each stream), and from low level timing i notice that the
> time to access a status register in the card sometimes goes up in the
> sky (I have measured well over 10us under heavy load, whereas the
> normal time is in the order of 0.5-1us).
>
> 10us is a fairly long time, and while i can explain it easily (there
> are 4 active cards in the system, each one with a transmit, receive
> and control engines trying to access the PCI bus -- and there are
> two bridges between the CPU and the card), i wonder if the CPU can
> potentially wait forever to get hold of the bus, or it eventually
> times out. If so, how can i tell that the operation failed ?
Rough guess, an NMI? Afaik this is the problem, if the bus hangs it
can wedge the CPU unless a higher priority non-masked interrupt
somehow makes it across the bus. Afaik this is what a watchdog
timer is for.
--
-Alfred Perlstein [[EMAIL PROTECTED]]
'Instead of asking why a piece of software is using "1970s technology,"
start asking why software is ignoring 30 years of accumulated wisdom.'
http://www.morons.org/rants/gpl-harmful.php3
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