Michael Schnell schrieb: > >> We don't need wait to synchronize caches. It will be done by hardware. > Right. but waiting performed by the hardware does not take less long > than waiting performed by software :-) . >> And i think synchronize cache with ram don't eat hundreads clock cycles. > In all cashed that contain the memory location, the appropriate cache > line will be invalidated. Thus it needs to be reloaded from main memory > before it can be accessed by the processor. This might introduce a huge > delay in a processor a long time after the the locking instruction was > performed by some different processor.
The point is, it simply affects all processor. Its much better than an entercriticalsection but it is not only twice the time of a simply inc or whatever. _______________________________________________ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
