Dariusz Mazur wrote:
Florian Klaempfl pisze:
DarekM schrieb:
Florian Klaempfl pisze:
An if is unimportant, more important is the number of locked
operations,
especially on multi core systems they might eat hundreds of clock
cycles.
There are atomic operations, the should not eat much more than ordinal
INC or ADD,
If course they are. They require no more a bus lock as in 486 times but
a synchronization of all caches for this particular memory location.
We don't need wait to synchronize caches. It will be done by hardware.
ehm... according to your pdf:
For the P6 family processors, locked operations serialize all
outstanding load and store operations (that is, wait for them to
complete). This rule is also true for the Pentium 4 and Intel Xeon
processors, with one exception. Load operations that reference weakly
ordered memory types (such as the WC memory type) may not be serialized.
And i think synchronize cache with ram don't eat hundreads clock cycles.
I think it does, why else do we need cache ?
And CMPXCHG has automatic locking asserted, as normal instruction can't
persist so long (Intel don't mention about this)
This is also use to implement semaphores (suggest from Intel) , thus
should be save and fast.
first, yes, second, thats relative.
Marc
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