On 16 aug 2005, at 17:54, Jonas Maebe wrote:
wer and PowerPC have been sort of merged quite a while ago already
and use the same instruction set now (at least from a non-OS
developer point-of-view). But it's indeed quite probable that the
cache line size on a Power5 is larger than 32 bytes (the G5 was
derived from the Power4).
Power5 has mixed 128 (L2) 256 (L3) byte cache lines (slide 18):
http://www.cs.utexas.edu/users/cart/arch/fall03/KallaSlides.pdf
Not sure how this works with dcbz, but most definitely not in a way
it's used in the RTL.
Jonas
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