On Sun, Jun 22, 2025 at 10:24 PM Thompson, Matt (GSFC-610.1)[SCIENCE SYSTEMS AND APPLICATIONS INC] <matthew.thomp...@nasa.gov> wrote:
> All, > > > > I'm currently a bit confused and I'm hoping the gfortran gurus can help. > > > > To wit, I have a code on a system with both AMD EPYC (Milan) and Intel > Cascade Lake nodes. The code in question I build on the Milans with either > our "Release" flags: > > > > Fortran_FLAGS = -O3 -march=znver2 -mtune=generic -funroll-loops -g > -ffree-line-length-none > > -fno-range-check -Wno-missing-include-dirs -fbacktrace > -Wno-unused-dummy-argument > > -ffpe-trap=zero,overflow -fbacktrace -fallow-argument-mismatch > -fallow-invalid-boz > > -falign-commons -fPIC -pthread -pthread -fopenmp > > > > or our "Aggressive" flags: > > > > Fortran_FLAGS = -O2 -march=native -ffast-math -ftree-vectorize > -funroll-loops > > --param max-unroll-times=4 -mno-fma -ffree-line-length-none > -fno-range-check > > -Wno-missing-include-dirs -fbacktrace -Wno-unused-dummy-argument -g > -fbacktrace > > -fallow-argument-mismatch -fallow-invalid-boz -falign-commons -fPIC > -pthread -pthread -fopenmp > > > > The thing I'm a bit flummoxed by is that in both cases, a code built on > AMD Milan is running on Intel Cascade Lake. > > > I can sort of see how "-march=znver2 -mtune=generic" could maybe be > clamping down instructions enough to make it boring enough to run on both, > but how is "-march=native" doing that? > -march=znver2 enables all ISA features Zen2 supports, -mtune=generic tunes optimization to a blend that's good on both AMD/Intel but does not affect the ISA being used. When you use -march=native then you get all ISA features enabled from the machine you compile on - this should be only used when you run on that very same machine (or identical copies). Or if you know what you are doing. I guess you've identified the Zen2 ISA to be the common subset so I'd say the Aggressive flags should use -march=znver2 as well. Or possibly it was supposed to be used only when compiling/running on the same machine type. > > > Am I just very incorrect about how -march/-mtune work? Or am I just > incredibly lucky this code seems to be portable (i.e., my code just doesn't > get compiled with AMD-only instructions). > Possibly. > (Note: even more odd, the AMD and Intel runs with Release are zero-diff as > well. That sort of surprised me.) > Well, AMD and Intel are compatible, so I wouldn't expect any actual computation data differences (if that's what you mean). If you are unlucky you'd get SIGILL (illegal instruction) in case the CPU the code runs on doesn't support an instruction used. Richard. > Thanks, > > Matt > > > > > > > > > > [image: signature_2578197698] <http://www.ssaihq.com/> > > [image: Image] > > *Matt Thompson* > > *Lead Scientific Software Engineer/Supervisor* > > Global Modeling and Assimilation Office > > Science Systems and Applications, Inc. > > Code 610.1, 8800 Greenbelt Rd, Greenbelt, MD 20771 > > o: 301-614-6712 > > matthew.thomp...@nasa.gov > > > > >
