On 2020-03-15 13:05, Hendrik Leppkes wrote:
On Sun, Mar 15, 2020 at 8:12 AM Steve Lhomme <rob...@ycbcr.xyz> wrote:
Where is this struct specified? I don't see it in the latest released
Windows SDK.
It is not. It is reversed engineered from the existing structure and wild
guessing based on the HEVC Range Extension specs. The bits/fields are in the
same order as the specs. Then I tested some GUIDs that output non 4:2:0 pixel
formats on an Intel GPU that is known to decoder HEVC Range Extension.
Apparently NVIDIA doesn't provide DXVA GUIDs that output non 4:2:0 pixel
formats on GPUs that supposedly decode HEVC 444 (likley nvdec only). AMD
doesn't have such GPUs AFAIK.
So for now it's Intel only.
That seems very hackish for something thats otherwise cleanly based on
official specifications only. Maybe try to get them to release specs
for this instead?
From what I understand only MS publishes DXVA specs and it seems they
have no intention on doing one for HEVC Range Extension. That may be why
NVIDIA has not implemented it. I don't know if Intel is planning to
release a documentation.
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