> On March 13, 2020 3:46 PM Hendrik Leppkes <h.lepp...@gmail.com> wrote:
>
>
> On Fri, Mar 13, 2020 at 11:25 AM Steve Lhomme <rob...@ycbcr.xyz> wrote:
> >
> > Mimick the existing structure and add the extra fields from the Range
> > Extension
> > in a wrapping structure.
> >
> > The FF_DXVA2_WORKAROUND_HEVC_REXT is set by the decoder user to signal the
> > selected decoder is expecting this extended structure rather than the
> > default
> > one.
> > ---
> > libavcodec/d3d11va.h | 1 +
> > libavcodec/dxva2.h | 1 +
> > libavcodec/dxva2_hevc.c | 79 ++++++++++++++++++++++++++++++++++++++---
> > 3 files changed, 76 insertions(+), 5 deletions(-)
> >
> > diff --git a/libavcodec/d3d11va.h b/libavcodec/d3d11va.h
> > index 6816b6c1e6..68a69c372d 100644
> > --- a/libavcodec/d3d11va.h
> > +++ b/libavcodec/d3d11va.h
> > @@ -47,6 +47,7 @@
> >
> > #define FF_DXVA2_WORKAROUND_SCALING_LIST_ZIGZAG 1 ///< Work around for
> > Direct3D11 and old UVD/UVD+ ATI video cards
> > #define FF_DXVA2_WORKAROUND_INTEL_CLEARVIDEO 2 ///< Work around for
> > Direct3D11 and old Intel GPUs with ClearVideo interface
> > +#define FF_DXVA2_WORKAROUND_HEVC_REXT 4 ///< Signal the D3D11VA
> > decoder is using the HEVC Rext picture structure
> >
> > /**
> > * This structure is used to provides the necessary configurations and data
> > diff --git a/libavcodec/dxva2.h b/libavcodec/dxva2.h
> > index 22c93992f2..024999239d 100644
> > --- a/libavcodec/dxva2.h
> > +++ b/libavcodec/dxva2.h
> > @@ -47,6 +47,7 @@
> >
> > #define FF_DXVA2_WORKAROUND_SCALING_LIST_ZIGZAG 1 ///< Work around for
> > DXVA2 and old UVD/UVD+ ATI video cards
> > #define FF_DXVA2_WORKAROUND_INTEL_CLEARVIDEO 2 ///< Work around for
> > DXVA2 and old Intel GPUs with ClearVideo interface
> > +#define FF_DXVA2_WORKAROUND_HEVC_REXT 4 ///< Signal the DXVA2
> > decoder is using the HEVC Rext picture structure
> >
> > /**
> > * This structure is used to provides the necessary configurations and data
> > diff --git a/libavcodec/dxva2_hevc.c b/libavcodec/dxva2_hevc.c
> > index dbb701fb1c..98b3e74bd7 100644
> > --- a/libavcodec/dxva2_hevc.c
> > +++ b/libavcodec/dxva2_hevc.c
> > @@ -26,10 +26,47 @@
> > #include "hevc_data.h"
> > #include "hevcdec.h"
> >
> > +#pragma pack(push, 1)
> > +typedef struct
> > +{
> > + DXVA_PicParams_HEVC main;
> > +
> > + // HEVC Range Extension
> > + __C89_NAMELESS union {
> > + __C89_NAMELESS struct {
> > + UINT32 transform_skip_rotation_enabled_flag : 1;
> > + UINT32 transform_skip_context_enabled_flag : 1;
> > + UINT32 implicit_rdpcm_enabled_flag : 1;
> > + UINT32 explicit_rdpcm_enabled_flag : 1;
> > + UINT32 extended_precision_processing_flag : 1;
> > + UINT32 intra_smoothing_disabled_flag : 1;
> > + UINT32 high_precision_offsets_enabled_flag : 1;
> > + UINT32 persistent_rice_adaptation_enabled_flag : 1;
> > + UINT32 cabac_bypass_alignment_enabled_flag : 1;
> > + UINT32 cross_component_prediction_enabled_flag : 1;
> > + UINT32 chroma_qp_offset_list_enabled_flag : 1;
> > + UINT32 BitDepthLuma16 : 1; // TODO merge in ReservedBits5 if
> > not needed
> > + UINT32 BitDepthChroma16 : 1; // TODO merge in ReservedBits5 if
> > not needed
> > + UINT32 ReservedBits8 : 19;
> > + };
> > + UINT32 dwRangeExtensionFlags;
> > + };
> > +
> > + UCHAR diff_cu_chroma_qp_offset_depth;
> > + UCHAR chroma_qp_offset_list_len_minus1;
> > + UCHAR log2_sao_offset_scale_luma;
> > + UCHAR log2_sao_offset_scale_chroma;
> > + UCHAR log2_max_transform_skip_block_size_minus2;
> > + CHAR cb_qp_offset_list[6];
> > + CHAR cr_qp_offset_list[6];
> > +
> > +} DXVA_PicParams_HEVC_Rext;
> > +#pragma pack(pop)
> > +
>
> Where is this struct specified? I don't see it in the latest released
> Windows SDK.
It is not. It is reversed engineered from the existing structure and wild
guessing based on the HEVC Range Extension specs. The bits/fields are in the
same order as the specs. Then I tested some GUIDs that output non 4:2:0 pixel
formats on an Intel GPU that is known to decoder HEVC Range Extension.
Apparently NVIDIA doesn't provide DXVA GUIDs that output non 4:2:0 pixel
formats on GPUs that supposedly decode HEVC 444 (likley nvdec only). AMD
doesn't have such GPUs AFAIK.
So for now it's Intel only.
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