On 10/11/13 15:58 , andy pugh wrote: > On 11 October 2013 16:35, Sebastian Kuzminsky <[email protected]> wrote: >> >> And *then*, we can make that EPP driver pluggable so we can drop a >> BBB/PRU EPP driver in, and have it export the same interface to the >> higher-level drivers, and then both 7i43 and 7i90, and whatever other >> EPP-using drivers we have, would work. > > Actually, in this _specific_ scenario I suspect that EPP emulation on > the BBB to talk to the FPGA is possibly a silly thing anyway, because > what is happening in the FPGA is GPIO emulating EPP. It is possibly > more sensible to just set up a fast serial link from BBB to 7i43, and > use a different firmware on the FPGA that doesn't waste effort trying > to be a parallel port.
The 7i43 specifically is pretty well tied to EPP due to the CPLD that receives the FPGA firmware via EPP and flashes the FPGA. Possibly a future AnyIO board won't have this requirement. Or maybe we could do slow EPP by software-twiddling the GPIO pins to send the firmware, then do some smarter/simpler serial protocol over the same wires once the FPGA firware is in control. -- Sebastian Kuzminsky ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134071&iu=/4140/ostg.clktrk _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
