<snip> since I didn't find Jon's post on the interrupt process.
Some reading of pdp wiki, etc refreshes memory (slowly). There were 4 interrupt lines which gave only 4 levels of interrupt. Then interrupts were further arbitrated by the position of the interrupting board on the bus. IIRC : CPU slot 0: memory slot 1: disk controller slot 2: . . . slower or less demanding devices. The interrupt stack grew upward thru memory as the number of unprocessed interrupts increased. It would grow happily to 4095 (10) by which time it had overwritten small programs. ;-( Maybe the Unibus stack would page, I don't know. HTH Dave ------------------------------------------------------------------------------ _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
