On 11/15/2013 03:02 PM, Jesse Brandeburg wrote:
> On Thu, 14 Nov 2013 16:10:13 -0500
> Vlad Yasevich <[email protected]> wrote:
>
>> Hi all
>>
>> I was wondering what does HW do when the receive address register
>> is only partially written?  The reason I am wondering is that
>> it looks like most drivers have to program the receive address
>> register in 2 writes.  What happens if only 1 write happens?
>>
>> Should frames that just happen to match the "new" address still
>> be accepted?
>
> Hi Vlad, the AV (address valid) bit (bit 31) should be used to disable
> the RAR (RAH contains the AV bit) while it is being programmed.
>
> it does seem there is an itty bitty window where RAL is written with a
> new value and if that entry had a value already and an AV bit set it
> would possibly have a "bad" mac address for a very short while.  In
> practice the PCIe writes are posted and will likely effectively be
> submitted to hardware nanoseconds apart.
>
> I'll see what the owners here think.  Thanks for the heads up.
>

Hi Jesse

Thank for taking a look.  I saw the AV bit in RAH as well.  That's
what got me asking the question.  The data sheet says AV gets turns off 
on resets only.  So if the address is changing from one value to
another AV is still valid half way through the write just as you said.

The main reason I am asking is that in qemu we are working on completing
a feature where a change in guest mac address is propagated to the host
and the host can program that address to the nic card.  The debate
we have is when to do the notifications since we have 2 writes.
One approach was to do it when RAH was written.  If there is a 
requirement that RAH has to be written last, that's works great.
However, if RAL and RAH can be written in any order, that doesn't work
and we notify on every write. In this case, we could end up
notifying twice and possibly writing incomplete mac address to HW.  That 
seemed bad.  So I was wondering how does HW behaves.

Thanks
-vlad

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