On Thu, 14 Nov 2013 16:10:13 -0500 Vlad Yasevich <[email protected]> wrote:
> Hi all > > I was wondering what does HW do when the receive address register > is only partially written? The reason I am wondering is that > it looks like most drivers have to program the receive address > register in 2 writes. What happens if only 1 write happens? > > Should frames that just happen to match the "new" address still > be accepted? Hi Vlad, the AV (address valid) bit (bit 31) should be used to disable the RAR (RAH contains the AV bit) while it is being programmed. it does seem there is an itty bitty window where RAL is written with a new value and if that entry had a value already and an AV bit set it would possibly have a "bad" mac address for a very short while. In practice the PCIe writes are posted and will likely effectively be submitted to hardware nanoseconds apart. I'll see what the owners here think. Thanks for the heads up. ------------------------------------------------------------------------------ DreamFactory - Open Source REST & JSON Services for HTML5 & Native Apps OAuth, Users, Roles, SQL, NoSQL, BLOB Storage and External API Access Free app hosting. Or install the open source package on any LAMP server. Sign up and see examples for AngularJS, jQuery, Sencha Touch and Native! http://pubads.g.doubleclick.net/gampad/clk?id=63469471&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
