On Tue, 2013-10-08 at 07:10 +1100, Benjamin Herrenschmidt wrote: > On Mon, 2013-10-07 at 14:01 -0400, Tejun Heo wrote: > > I don't think the same race condition would happen with the loop. The > > problem case is where multiple msi(x) allocation fails completely > > because the global limit went down before inquiry and allocation. In > > the loop based interface, it'd retry with the lower number. > > > > As long as the number of drivers which need this sort of adaptive > > allocation isn't too high and the common cases can be made simple, I > > don't think the "complex" part of interface is all that important. > > Maybe we can have reserve / cancel type interface or just keep the > > loop with more explicit function names (ie. try_enable or something > > like that). > > I'm thinking a better API overall might just have been to request > individual MSI-X one by one :-) > > We want to be able to request an MSI-X at runtime anyway ... if I want > to dynamically add a queue to my network interface, I want it to be able > to pop a new arbitrary MSI-X.
Yes, this would be very useful. > And we don't want to lock drivers into contiguous MSI-X sets either. I don't think there's any such limitation now. The entries array passed to pci_enable_msix() specifies which MSI-X vectors the driver wants to enable. It's usually filled with 0..nvec-1 in order, but not always. And the IRQ numbers returned aren't usually contiguous either, on x86. Ben. > And for the cleanup ... well that's what the "pcim" functions are for, > we can just make MSI-X variants. -- Ben Hutchings, Staff Engineer, Solarflare Not speaking for my employer; that's the marketing department's job. They asked us to note that Solarflare product names are trademarked. ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134071&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
