On 10/27/26 8:14 AM, Ishu Brar via B4 Relay wrote: > From: Ishu Brar <[email protected]> > > No protect entry covers the range from 0x1c800 to 0x1e7ff: the entry > at 0x1a800 ends at 0x1c7ff and the next one starts at 0x1f400. The range > holds GMU registers, among them GMU_NMI_CONTROL_STATUS (0x1cbf0), > GMU_BOOT_SLUMBER_OPTION (0x1cbf8), the GX and MX vote indexes (0x1cbf9, > 0x1cbfa), the DCVS option, setting and return registers (0x1cbfc to > 0x1cbff) and GMU_CORE_FW_VERSION (0x1d3f8), see a6xx_gmu.xml. > > Add the range as no read/write to the A650 protect list, which A620 and > A650 share, so that these registers are reserved as well. This follows > Konrad Dybcio's suggestion; the downstream kgsl protect table of the > OnePlus Nord (a620_protected_regs) has no entry for this range, so there > is no downstream reference for it. > > The list is also used by A621, A623, A702 and A704, which I could not > test. Tested on A620 only (OnePlus Nord, a 7.3 based tree): a Vulkan > workload ran across GPU frequency changes without protect, fault or GMU > errors. A write into the range being rejected was not tested. > > Suggested-by: Konrad Dybcio <[email protected]> > Signed-off-by: Ishu Brar <[email protected]> > ---
Reviewed-by: Konrad Dybcio <[email protected]> Konrad
