From: Ishu Brar <[email protected]> No protect entry covers the range from 0x1c800 to 0x1e7ff: the entry at 0x1a800 ends at 0x1c7ff and the next one starts at 0x1f400. The range holds GMU registers, among them GMU_NMI_CONTROL_STATUS (0x1cbf0), GMU_BOOT_SLUMBER_OPTION (0x1cbf8), the GX and MX vote indexes (0x1cbf9, 0x1cbfa), the DCVS option, setting and return registers (0x1cbfc to 0x1cbff) and GMU_CORE_FW_VERSION (0x1d3f8), see a6xx_gmu.xml.
Add the range as no read/write to the A650 protect list, which A620 and A650 share, so that these registers are reserved as well. This follows Konrad Dybcio's suggestion; the downstream kgsl protect table of the OnePlus Nord (a620_protected_regs) has no entry for this range, so there is no downstream reference for it. The list is also used by A621, A623, A702 and A704, which I could not test. Tested on A620 only (OnePlus Nord, a 7.3 based tree): a Vulkan workload ran across GPU frequency changes without protect, fault or GMU errors. A write into the range being rejected was not tested. Suggested-by: Konrad Dybcio <[email protected]> Signed-off-by: Ishu Brar <[email protected]> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 6cdc3f5a2583..c93de04bb187 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -576,6 +576,7 @@ static const u32 a650_protect_regs[] = { A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), A6XX_PROTECT_NORDWR(0x18400, 0x1fff), A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), + A6XX_PROTECT_NORDWR(0x1c800, 0x1fff), A6XX_PROTECT_NORDWR(0x1f400, 0x0443), A6XX_PROTECT_RDONLY(0x1f844, 0x007b), A6XX_PROTECT_NORDWR(0x1f887, 0x001b), -- 2.56.0
