Add device tree overlay for the Good Display GDEY042T81 4.2" e-paper panel connected to the AM62L3 EVM via SPI.
The overlay configures SPI1 with the SSD1683-based GDEY042T81 panel at 2MHz, with reset, busy, and DC GPIOs connected to MCU GPIO0. Signed-off-by: Devarsh Thakkar <[email protected]> --- Changes from v1: - No changes: Minor improvements to DTS overlay structure NOTE: This should only be merged post driver is merged arch/arm64/boot/dts/ti/Makefile | 6 ++ .../ti/k3-am62l3-evm-epaper-gdey042t81.dtso | 96 +++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper-gdey042t81.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 795978e962ee..90e7a687ca86 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -82,6 +82,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62l3-beaglebadge.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb +# Overlays for AM62Lx EVM +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm-epaper-gdey042t81.dtbo + # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb @@ -319,6 +322,8 @@ k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \ k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am62a7-sk-hdmi-audio-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-hdmi-audio.dtbo +k3-am62l3-evm-epaper-gdey042t81-dtbs := k3-am62l3-evm.dtb \ + k3-am62l3-evm-epaper-gdey042t81.dtbo k3-am62p5-sk-csi2-imx219-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-imx219.dtbo k3-am62p5-sk-csi2-ov5640-dtbs := k3-am62p5-sk.dtb \ @@ -458,6 +463,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-csi2-imx219.dtb \ k3-am62a7-sk-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ + k3-am62l3-evm-epaper-gdey042t81.dtb \ k3-am62p5-sk-csi2-imx219.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper-gdey042t81.dtso b/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper-gdey042t81.dtso new file mode 100644 index 000000000000..50975a2cdd2a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm-epaper-gdey042t81.dtso @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * DT Overlay for GoodDisplay GDEY042T81 4.2" E-Paper Display on AM62L3 EVM + * + * The GDEY042T81 is a 400x300 black-and-white e-paper panel driven by a + * Solomon SSD1683 controller, connected via SPI1 on the AM62L3 EVM + * expansion header. + * + * Pin mapping (AM62L3 EVM expansion header): + * P5 --> BUSY (GPMC0_AD0.GPIO0_31) + * P26 --> RST (GPMC0_AD1.GPIO0_16) + * P27 --> CLK (GPMC0_AD5.SPI1_CLK) + * P28 --> DC (GPMC0_AD2.GPIO0_17) + * P29 --> DAT (GPMC0_AD3.SPI1_D1 / MOSI) + * P30 --> CS (GPMC0_AD4.SPI1_CS0) + * + * The GPMC0_AD[0:5] pins are multiplexed for SPI1 and GPIO use; GPMC0 is + * already disabled by default in the SoC DTSI. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "k3-pinctrl.h" + +&pmx0 { + dc_pins_default: epaper-dc-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0080, PIN_OUTPUT, 7) /* (K22) GPMC0_AD2.GPIO0_17 */ + >; + }; + + rst_pins_default: epaper-rst-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x007c, PIN_OUTPUT, 7) /* (L23) GPMC0_AD1.GPIO0_16 */ + >; + }; + + busy_pins_default: epaper-busy-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00b8, PIN_INPUT, 7) /* (L21) GPMC0_AD0.GPIO0_31 */ + >; + }; + + main_spi1_pins_default: main-spi1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x008c, PIN_OUTPUT, 4) /* (H22) GPMC0_AD5.SPI1_CLK */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 4) /* (K23) GPMC0_AD4.SPI1_CS0 */ + AM62LX_IOPAD(0x0084, PIN_OUTPUT, 4) /* (J23) GPMC0_AD3.SPI1_D1 */ + >; + }; + + fet_sel_pins_default: epaper-fet-sel-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (E13) SPI0_CLK.GPIO0_89 */ + >; + }; +}; + +/* Drive GPIO0_89 high to select the SPI1 path on the VOUT0 FET switch */ +&gpio0 { + fet-sel-hog { + gpio-hog; + gpios = <89 0>; + output-high; + line-name = "GPIO_EXP_CONN_FET_SEL"; + }; +}; + +&gpmc0 { + status = "disabled"; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>, <&fet_sel_pins_default>; + status = "okay"; + + gdey042t81: display@0 { + compatible = "gooddisplay,gdey042t81", "solomon,ssd1683"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&dc_pins_default>, + <&rst_pins_default>, + <&busy_pins_default>; + spi-max-frequency = <2000000>; + reset-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + busy-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; +}; -- 2.39.1
