On Wed, Aug 26, 2026 at 11:24:59PM +0500, Saim Shujah wrote:
> Hardware can consume an active-frame CTL flush while the cached software
> pending-flush mask retains the submitted bits. Video-mode disable stops the
> timing engine before physical cleanup, which then adds teardown bits to the
> stale cached mask.
>
> The teardown trigger can replay source-pipe bits after timing
> stops, leaving one pending and preventing the first commit after re-enable.
>
> Clear the cached pending-flush bookkeeping before constructing the teardown
> state. clear_pending_flush() updates software bookkeeping only; it does not
> write the hardware CTL_FLUSH register.
>
> Fixes: 22cb02bc96ff ("drm/msm/disp/dpu: reset the datapath after timing
> engine disable")
> Cc: [email protected]
> Signed-off-by: Saim Shujah <[email protected]>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
>
--
With best wishes
Dmitry
