On Fri, Aug 28, 2026 at 11:54:40AM +0500, Saim Shujah wrote:
> dpu_hw_ctl_clear_pending_flush() resets the cached per-block state after a
> flush transaction, but misses pending_periph_flush_mask.
>
> The peripheral flush updater accumulates interface bits in this mask. A
> later transaction which sets the top-level peripheral flush bit can write
> stale interface bits to CTL_PERIPH_FLUSH together with the current state.
>
> Peripheral flush support was added after the helper started clearing every
> individual pending flush mask. Clear the peripheral mask together with the
> other cached child masks.
>
> Fixes: 64f7b81f0358 ("drm/msm/dpu: add support of new peripheral flush
> mechanism")
> Cc: [email protected]
> Signed-off-by: Saim Shujah <[email protected]>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
>
--
With best wishes
Dmitry
