On Thu, Apr 02, 2026 at 01:34:13PM +0530, Ankit Nautiyal wrote: > Introduce a helper to check if Panel Replay has Async Video Timing support > during PR Active state. > > Signed-off-by: Ankit Nautiyal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_psr.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 2f1b48cd8efd..782e839b7396 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -4623,3 +4623,11 @@ bool intel_psr_use_trans_push(const struct > intel_crtc_state *crtc_state) > > return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; > } > + > +bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp) > +{ > + struct intel_connector *connector = intel_dp->attached_connector; > +
I think we also need to confirm here that panel replay itself is supported by the sink. Otherwise this bit will for sure be zero and then we'll think that we need to transmit AS SDP even for non-PR sinks. > + return > !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] > & > + DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); > +} > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h > b/drivers/gpu/drm/i915/display/intel_psr.h > index 394b641840b3..29723e63888f 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp > *intel_dp, > struct intel_crtc_state *crtc_state); > int intel_psr_min_guardband(struct intel_crtc_state *crtc_state); > bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state); > +bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp); > > #endif /* __INTEL_PSR_H__ */ > -- > 2.45.2 -- Ville Syrjälä Intel
