On 3/30/2026 11:59 PM, Ville Syrjälä wrote:
On Mon, Mar 30, 2026 at 09:36:49AM +0530, Ankit Nautiyal wrote:
DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD
0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2
(AS SDP v2), which allows the source to set the version in HB2[4:0] and the
payload length in HB3[5:0] of the AS SDP header.
DP v2.1 SCR also adds a bit for Async Video Timing during Panel Replay, in
Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is cleared, the
sink supports asynchronous video timing while in a Panel Replay Active
state. The spec mandates that such sinks shall support AS SDP v2.
Infer AS SDP v2 support from these capabilities and store it in
struct intel_dp for use by subsequent feature enablement changes.
v2:
- Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to
determine AS SDP v2 support. (Ville)
Signed-off-by: Ankit Nautiyal <[email protected]>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2496db1642a..efc609eef4f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1870,6 +1870,7 @@ struct intel_dp {
/* connector directly attached - won't be use for modeset in mst world
*/
struct intel_connector *attached_connector;
bool as_sdp_supported;
+ bool as_sdp_v2_supported;
struct drm_dp_tunnel *tunnel;
bool tunnel_suspended:1;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f9bfb07f0205..b2007ffe18bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6301,6 +6301,40 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
false);
}
+static bool
+intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
+{
+ u8 rx_features;
+ u8 pr_caps;
+
+ /*
+ * The DP spec does not explicitly provide the AS SDP v2 capability.
+ * So based on the DP v2.1 SCR, we infer it from the following bits:
+ *
+ * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for
+ * FAVT, which is explicitly defined to use AS SDP v2.
+ *
+ * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR cleared indicates support
+ * for Async Video timing in PR active and the spec mandates that such
+ * sinks shall support AS SDP v2.
+ */
+ if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+ DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+ &rx_features) == 1) {
+ if (rx_features &
DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED)
+ return true;
+ }
+
+ if (drm_dp_dpcd_read_byte(&intel_dp->aux,
+ DP_PANEL_REPLAY_CAP_CAPABILITY,
+ &pr_caps) == 1) {
+ if (!(pr_caps &
DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
That seems to be backwards. If the sink requires AS SDP
then it will set the bit.
Hmm.. I indeed got it backwards, you are right.
If Async Video timing is supported then re-set the bit. But in that case
AS SDP is not required.
So reset means AS SDP not required; bit set means it is required.
Thanks, I will correct this in next version.
Regards,
Ankit
+ return true;
+ }
+
+ return false;
+}
+
static void
intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
{
@@ -6308,6 +6342,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
+
+ intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
+
intel_dp_sink_supports_as_sdp_v2(intel_dp);
}
static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
--
2.45.2
