Hi Chris, On Mon, 24 Nov 2025 at 14:10, Chris Brandt <[email protected]> wrote: > Convert the limited MIPI clock calculations to a full range of settings > based on math including H/W limitation validation. > Since the required DSI division setting must be specified from external > sources before calculations, expose a new API to set it. > > Signed-off-by: Chris Brandt <[email protected]> > Reviewed-by: Biju Das <[email protected]> > Tested-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]> i.e. will queue in renesas-clk for v6.20. > --- a/include/linux/clk/renesas.h > +++ b/include/linux/clk/renesas.h > @@ -18,6 +18,11 @@ struct device; > struct device_node; > struct generic_pm_domain; > > +enum { > + PLL5_TARGET_DPI, > + PLL5_TARGET_DSI > +}; While applying, I will move this just above the functions it applies to... > + > void cpg_mstp_add_clk_domain(struct device_node *np); > #ifdef CONFIG_CLK_RENESAS_CPG_MSTP > int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device > *dev); > @@ -177,4 +182,10 @@ static inline bool rzv2h_get_pll_divs_pars(const struct > rzv2h_pll_limits *limits > } > #endif > > +#ifdef CONFIG_CLK_RZG2L > +void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target); > +#else > +static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { } > +#endif > + ... and this part up, just before the RZ/V2H parts. > #endif Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
