The OVR_REG_FLD_MOD function takes the start and end bits as parameter
and will generate a mask out of them.
This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.
Let's change OVR_REG_FLD_MOD to take the mask as an argument instead,
and let the caller create the mask. Eventually, this mask will be moved
to a define.
Signed-off-by: Maxime Ripard <mrip...@kernel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c
b/drivers/gpu/drm/tidss/tidss_dispc.c
index
c5cad1ddcccfbf1d0b6fb53773bb3aff428ef493..99d3a84a5b40e1e791300199d6b3da9a12d11f80
100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -645,17 +645,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32
hw_videoport)
u32 _reg = dispc_vp_read(_dispc, _vp, _idx); \
FIELD_MODIFY((mask), &_reg, (val)); \
dispc_vp_write(_dispc, _vp, _idx, _reg); \
})
-#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \
+#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, mask) \
({ \
struct dispc_device *_dispc = (dispc); \
u32 _ovr = (ovr); \
u32 _idx = (idx); \
u32 _reg = dispc_ovr_read(_dispc, _ovr, _idx); \
- FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \
+ FIELD_MODIFY((mask), &_reg, (val)); \
dispc_ovr_write(_dispc, _ovr, _idx, _reg); \
})
static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport)
{
@@ -1483,29 +1483,29 @@ static void dispc_am65x_ovr_set_plane(struct
dispc_device *dispc,
u32 x, u32 y, u32 layer)
{
u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
- hw_id, 4, 1);
- OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
- x, 17, 6);
- OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
- y, 30, 19);
+ hw_id, GENMASK(4, 1));
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x,
+ GENMASK(17, 6));
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y,
+ GENMASK(30, 19));
}
static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
u32 hw_plane, u32 hw_videoport,
u32 x, u32 y, u32 layer)
{
u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
- hw_id, 4, 1);
- OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
- x, 13, 0);
- OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
- y, 29, 16);
+ hw_id, GENMASK(4, 1));
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x,
+ GENMASK(13, 0));
+ OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y,
+ GENMASK(29, 16));
}
void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
u32 hw_videoport, u32 x, u32 y, u32 layer)
{
@@ -1536,11 +1536,11 @@ void dispc_ovr_enable_layer(struct dispc_device *dispc,
{
if (dispc->feat->subrev == DISPC_K2G)
return;
OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
- !!enable, 0, 0);
+ !!enable, GENMASK(0, 0));
}
/* CSC */
enum csc_ctm {
CSC_RR, CSC_RG, CSC_RB,
--
2.50.1
