The VID_REG_GET function takes the start and end bits as parameter and
will generate a mask out of them.
This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.
Let's change VID_REG_GET to take the mask as an argument instead, and
let the caller create the mask. Eventually, this mask will be moved to a
define.
Signed-off-by: Maxime Ripard <mrip...@kernel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c
b/drivers/gpu/drm/tidss/tidss_dispc.c
index
1b2791e8c04c463552ad370f48dce8eae5b94702..b4928cfbb6f7ca9a03371c5e599e2029baae333f
100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -619,13 +619,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32
hw_videoport)
u32 _reg = dispc_read(_dispc, _idx); \
FIELD_MODIFY((mask), &_reg, (val)); \
dispc_write(_dispc, _idx, _reg); \
})
-#define VID_REG_GET(dispc, hw_plane, idx, start, end) \
- ((u32)FIELD_GET(GENMASK((start), (end)), \
- dispc_vid_read((dispc), (hw_plane), (idx))))
+#define VID_REG_GET(dispc, hw_plane, idx, mask)
\
+ ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx))))
#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \
({ \
struct dispc_device *_dispc = (dispc); \
u32 _hw_plane = (hw_plane); \
@@ -2307,11 +2306,12 @@ void dispc_plane_enable(struct dispc_device *dispc, u32
hw_plane, bool enable)
VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
}
static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
{
- return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);
+ return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS,
+ GENMASK(15, 0));
}
static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc,
u32 hw_plane, u32 low, u32 high)
{
--
2.50.1
