From: Jessica Zhang <jessica.zh...@oss.qualcomm.com>

Update Qualcomm DT files in order to declare extra stream pixel clocks
used on these platforms to support DisplayPort MST.

Signed-off-by: Jessica Zhang <jessica.zh...@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi   | 34 ++++++++++++----
 arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++--
 arch/arm64/boot/dts/qcom/sc8180x.dtsi  | 20 +++++++---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-----------
 arch/arm64/boot/dts/qcom/sdm845.dtsi   | 15 +++++--
 arch/arm64/boot/dts/qcom/sm8150.dtsi   | 10 +++--
 arch/arm64/boot/dts/qcom/sm8250.dtsi   | 10 +++--
 arch/arm64/boot/dts/qcom/sm8350.dtsi   | 10 +++--
 arch/arm64/boot/dts/qcom/sm8450.dtsi   | 10 +++--
 arch/arm64/boot/dts/qcom/sm8550.dtsi   | 10 +++--
 arch/arm64/boot/dts/qcom/sm8650.dtsi   | 10 +++--
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++-----
 12 files changed, 171 insertions(+), 70 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi 
b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 
64f5378c6a4770cee2c7d76cde1098d7df17a24a..1c7d3a251d9255111e9fc2de3e9c75c151490ba4
 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -4703,15 +4703,28 @@ mdss0_dp0: displayport-controller@af54000 {
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel",
+                                             "stream_2_pixel",
+                                             "stream_3_pixel";
                                assigned-clocks = <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss0_dp0_phy 0>, 
<&mdss0_dp0_phy 1>;
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp0_phy 0>,
+                                                        <&mdss0_dp0_phy 1>,
+                                                        <&mdss0_dp0_phy 1>,
+                                                        <&mdss0_dp0_phy 1>,
+                                                        <&mdss0_dp0_phy 1>;
                                phys = <&mdss0_dp0_phy>;
                                phy-names = "dp";
 
@@ -4782,15 +4795,20 @@ mdss0_dp1: displayport-controller@af5c000 {
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
                                         <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
-                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+                                        <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
                                assigned-clocks = <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
-                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss0_dp1_phy 0>, 
<&mdss0_dp1_phy 1>;
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp1_phy 0>,
+                                                        <&mdss0_dp1_phy 1>,
+                                                        <&mdss0_dp1_phy 1>;
                                phys = <&mdss0_dp1_phy>;
                                phy-names = "dp";
 
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi 
b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index 
38f7869616ff01ece3799ced15c39375d629e364..62bd535d7f14bed10fae329b20ac97cb63f3761b
 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -2144,16 +2144,20 @@ mdss_dp0: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_dp_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_dp_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_dp_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi 
b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 
836ac94551478fd728b1229616bbc6494cee336f..e5c8d447c4f89481644c8e45582504cd3b43d415
 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3239,16 +3239,20 @@ mdss_dp0: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
-                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_prim_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_prim_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_prim_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
@@ -3317,16 +3321,20 @@ mdss_dp1: displayport-controller@ae98000 {
                                         <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
                                         <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
-                                        <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_sec_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_sec_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_sec_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 
421693208af0d5baeaa14ba2bbf29cbbc677e732..ad04868763d00221ed9939c76132977b83762cd7
 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 {
                                         <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc0 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc0 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc0 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc0 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface", "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc0 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc0 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                                                 <&dispcc0 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_0_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_0_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_0_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 {
                                         <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
                                         <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
                                         <&dispcc0 
DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
-                                        <&dispcc0 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+                                        <&dispcc0 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+                                        <&dispcc0 
DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
                                clock-names = "core_iface", "core_aux",
                                              "ctrl_link",
-                                             "ctrl_link_iface", "stream_pixel";
+                                             "ctrl_link_iface", "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc0 
DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
-                                                 <&dispcc0 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+                                                 <&dispcc0 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
                                         <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
                                         <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
                                         <&dispcc0 
DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
-                                        <&dispcc0 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+                                        <&dispcc0 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+                                        <&dispcc0 
DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
                                clock-names = "core_iface", "core_aux",
                                              "ctrl_link",
-                                             "ctrl_link_iface", "stream_pixel";
+                                             "ctrl_link_iface", "stream_pixel",
+                                             "stream_1_pixel";
                                interrupt-parent = <&mdss0>;
                                interrupts = <14>;
                                phys = <&mdss0_dp2_phy>;
@@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
                                power-domains = <&rpmhpd SC8280XP_MMCX>;
 
                                assigned-clocks = <&dispcc0 
DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
-                                                 <&dispcc0 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss0_dp2_phy 0>, 
<&mdss0_dp2_phy 1>;
+                                                 <&dispcc0 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+                                                 <&dispcc0 
DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss0_dp2_phy 0>,
+                                                        <&mdss0_dp2_phy 1>,
+                                                        <&mdss0_dp2_phy 1>;
                                operating-points-v2 = <&mdss0_dp2_opp_table>;
 
                                #sound-dai-cells = <0>;
@@ -5675,10 +5688,12 @@ mdss1_dp0: displayport-controller@22090000 {
                                         <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc1 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc1 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc1 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc1 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface", "core_aux",
                                              "ctrl_link",
-                                             "ctrl_link_iface", "stream_pixel";
+                                             "ctrl_link_iface", "stream_pixel",
+                                             "stream_1_pixel";
                                interrupt-parent = <&mdss1>;
                                interrupts = <12>;
                                phys = <&mdss1_dp0_phy>;
@@ -5686,8 +5701,11 @@ mdss1_dp0: displayport-controller@22090000 {
                                power-domains = <&rpmhpd SC8280XP_MMCX>;
 
                                assigned-clocks = <&dispcc1 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc1 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss1_dp0_phy 0>, 
<&mdss1_dp0_phy 1>;
+                                                 <&dispcc1 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc1 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss1_dp0_phy 0>,
+                                                        <&mdss1_dp0_phy 1>,
+                                                        <&mdss1_dp0_phy 1>;
                                operating-points-v2 = <&mdss1_dp0_opp_table>;
 
                                #sound-dai-cells = <0>;
@@ -5750,10 +5768,12 @@ mdss1_dp1: displayport-controller@22098000 {
                                         <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
                                         <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
                                         <&dispcc1 
DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
-                                        <&dispcc1 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+                                        <&dispcc1 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+                                        <&dispcc1 
DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
                                clock-names = "core_iface", "core_aux",
                                              "ctrl_link",
-                                             "ctrl_link_iface", "stream_pixel";
+                                             "ctrl_link_iface", "stream_pixel",
+                                             "stream_1_pixel";
                                interrupt-parent = <&mdss1>;
                                interrupts = <13>;
                                phys = <&mdss1_dp1_phy>;
@@ -5761,8 +5781,11 @@ mdss1_dp1: displayport-controller@22098000 {
                                power-domains = <&rpmhpd SC8280XP_MMCX>;
 
                                assigned-clocks = <&dispcc1 
DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
-                                                 <&dispcc1 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss1_dp1_phy 0>, 
<&mdss1_dp1_phy 1>;
+                                                 <&dispcc1 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+                                                 <&dispcc1 
DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss1_dp1_phy 0>,
+                                                        <&mdss1_dp1_phy 1>,
+                                                        <&mdss1_dp1_phy 1>;
                                operating-points-v2 = <&mdss1_dp1_opp_table>;
 
                                #sound-dai-cells = <0>;
@@ -5825,10 +5848,12 @@ mdss1_dp2: displayport-controller@2209a000 {
                                         <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
                                         <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
                                         <&dispcc1 
DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
-                                        <&dispcc1 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+                                        <&dispcc1 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+                                        <&dispcc1 
DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
                                clock-names = "core_iface", "core_aux",
                                              "ctrl_link",
-                                             "ctrl_link_iface", "stream_pixel";
+                                             "ctrl_link_iface", "stream_pixel",
+                                             "stream_1_pixel";
                                interrupt-parent = <&mdss1>;
                                interrupts = <14>;
                                phys = <&mdss1_dp2_phy>;
@@ -5836,8 +5861,11 @@ mdss1_dp2: displayport-controller@2209a000 {
                                power-domains = <&rpmhpd SC8280XP_MMCX>;
 
                                assigned-clocks = <&dispcc1 
DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
-                                                 <&dispcc1 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss1_dp2_phy 0>, 
<&mdss1_dp2_phy 1>;
+                                                 <&dispcc1 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+                                                 <&dispcc1 
DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss1_dp2_phy 0>,
+                                                        <&mdss1_dp2_phy 1>,
+                                                        <&mdss1_dp2_phy 1>;
                                operating-points-v2 = <&mdss1_dp2_opp_table>;
 
                                #sound-dai-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 
828b55cb6baf10458feae8f53c04663ef958601e..816987906ca51b8c7eb834d8b850839941eadb6b
 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4656,12 +4656,19 @@ mdss_dp: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
-                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
-                               clock-names = "core_iface", "core_aux", 
"ctrl_link",
-                                             "ctrl_link_iface", "stream_pixel";
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+                               clock-names = "core_iface",
+                                             "core_aux",
+                                             "ctrl_link",
+                                             "ctrl_link_iface",
+                                             "stream_pixel",
+                                             "stream_1_pixel";
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
                                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
                                phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi 
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 
4b347ee3244100a4db515515b73575383c5a0cb7..e0beb5373cdc8ff92f165d7a971f8f7dce31bca8
 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3890,16 +3890,20 @@ mdss_dp: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
-                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi 
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 
244339cfbed5c32708c282de18f5655535e2ff45..272b41214ab31edd2c0c695cf294f0959167585a
 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4771,16 +4771,20 @@ mdss_dp: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
-                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 
9a4207ead6156333b8b6030fb0fbc1d215948041..136f40a3b9767133d6a4fe52753530bccced3391
 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2876,16 +2876,20 @@ mdss_dp: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
-                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi 
b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 
2baef6869ed7c17efb239e86013c15ef6ef5f48f..1b482dc5f574acd5ea938c9953a35164e51c6cb3
 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi 
b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 
38d139d1dd4a994287c03d064ca01d59a11ac771..2d085680afd1bed2bd2477c21ae4b798efe6a066
 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3755,16 +3755,20 @@ mdss_dp0: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_dp_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_dp_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_dp_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi 
b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 
d6794901f06b50e8629afd081cb7d229ea342f84..887b2ea055e8d969ba9ad07e738dcb6feccc0e61
 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5657,16 +5657,20 @@ mdss_dp0: displayport-controller@af54000 {
                                         <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_dp_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_dp_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_dp_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                operating-points-v2 = <&dp_opp_table>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 
f293b13ecc0ce426661187ac793f147d12434fcb..7c5f6c101ac10ce6fbc5eead177246ce77c668bf
 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5338,16 +5338,20 @@ mdss_dp0: displayport-controller@ae90000 {
                                         <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_ss0_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_ss0_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_ss0_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                operating-points-v2 = <&mdss_dp0_opp_table>;
@@ -5421,16 +5425,20 @@ mdss_dp1: displayport-controller@ae98000 {
                                         <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_ss1_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_ss1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_ss1_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                operating-points-v2 = <&mdss_dp1_opp_table>;
@@ -5504,16 +5512,20 @@ mdss_dp2: displayport-controller@ae9a000 {
                                         <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
                                         <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
                                         <&dispcc 
DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
-                                        <&dispcc 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+                                        <&dispcc 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+                                        <&dispcc 
DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
                                clock-names = "core_iface",
                                              "core_aux",
                                              "ctrl_link",
                                              "ctrl_link_iface",
-                                             "stream_pixel";
+                                             "stream_pixel",
+                                             "stream_1_pixel";
 
                                assigned-clocks = <&dispcc 
DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
-                                                 <&dispcc 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+                                                 <&dispcc 
DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
                                assigned-clock-parents = <&usb_1_ss2_qmpphy 
QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_1_ss2_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>,
                                                         <&usb_1_ss2_qmpphy 
QMP_USB43DP_DP_VCO_DIV_CLK>;
 
                                operating-points-v2 = <&mdss_dp2_opp_table>;

-- 
2.47.2

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