On Tue, 3 Jun 2025 at 18:50, Christian König <christian.koe...@amd.com> wrote: > > On 6/3/25 09:52, David Airlie wrote: > > On Tue, Jun 3, 2025 at 5:47 PM Christian König <christian.koe...@amd.com> > > wrote: > >> > >> On 6/2/25 22:40, Dave Airlie wrote: > >>> From: Dave Airlie <airl...@redhat.com> > >>> > >>> Currently you can't see per-device numa aware pools properly. > >>> > >>> Cc: Christian König <christian.koe...@amd.com> > >>> Signed-off-by: Dave Airlie <airl...@redhat.com> > >> > >> Reviewed-by: Christian König <christian.koe...@amd.com> > >> > >> Any follow up patch to wire this up in amdgpu? > > > > Just seems to work, at least I tested it on a 4 node MI300A system > > this morning and > > > > /sys/kernel/debug/dri/*/ttm_page_pool seems to reflect the correct pools. > > Yeah that should work, but there is also the mode where we allocated the pool > in the driver because the MI300 has connections to multiple NUMA nodes. > > See amdgpu_ttm_tt_populate(). > > I will take care of this after that patch here lands. >
I've landed this in drm-misc-next. Thanks, Dave.
