On 5/14/25 9:23 PM, Dmitry Baryshkov wrote:
> On Wed, May 14, 2025 at 05:10:33PM +0200, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
>>
>> The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of
>> swizzling) is what we want on this platform (and others with a UBWC
>> 1.0 encoder).
>>
>> Fix it to make mesa happy (the hardware doesn't care about the 2 higher
>> bits, as they weren't consumed on this platform).
>>
>> Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
>> ---
>> drivers/soc/qcom/ubwc_config.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
>> index
>> 9caecd071035ccb03f14464e9b7129ba34a7f862..96b94cf01218cce2dacdba22c7573ba6148fcdd1
>> 100644
>> --- a/drivers/soc/qcom/ubwc_config.c
>> +++ b/drivers/soc/qcom/ubwc_config.c
>> @@ -103,7 +103,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data = {
>> static const struct qcom_ubwc_cfg_data sm6125_data = {
>> .ubwc_enc_version = UBWC_1_0,
>> .ubwc_dec_version = UBWC_3_0,
>> - .ubwc_swizzle = 1,
>> + .ubwc_swizzle = 7,
>> .highest_bank_bit = 14,
>> };
>
> Add a comment and squash into the patch 1.
I don't think that's a good idea, plus this series should be merged
together anyway
Konrad
