From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
In preparation to resolve the issue of hardcoding HBB, throw a warning
if the value is being overwritten in the GPU driver.
The HBB value is directly correlated with the memory configuration.
On platforms where more than one is supported, the value must differ
for proper functioning of the hardware, but it also must be consistent
across all UBWC producers/consumers.
On platforms supporting only a single DRAM setup, the value may still
be wrong, or at least inconsistent.
Print a warning to help catch such cases, until we declare full trust
to the central database.
Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index
eaf468b67f97ff153e92a73a45581228fcf75e46..ab812338739568d5908ca439e5c53e230a02de5d
100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -637,6 +637,10 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a702(gpu))
cfg->highest_bank_bit = 14;
+ if (cfg->highest_bank_bit != common_cfg->highest_bank_bit)
+ DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs
%u (UBWC_CFG)\n",
+ cfg->highest_bank_bit,
common_cfg->highest_bank_bit);
+
gpu->ubwc_config = &gpu->_ubwc_config;
return 0;
--
2.49.0
