On 4/14/2025 4:31 PM, Konrad Dybcio wrote:
> On 2/27/25 9:07 PM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_ji...@quicinc.com>
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang <quic_ji...@quicinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com>
>> ---
>
> [...]
>
>> + gmu: gmu@3d6a000 {
>> + compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
>> + reg = <0x0 0x03d6a000 0x0 0x34000>,
>
> size = 0x26000 so that it doesn't leak into GPU_CC
We dump GPUCC regs into snapshot!
>
>> + <0x0 0x03de0000 0x0 0x10000>,
>> + <0x0 0x0b290000 0x0 0x10000>;
>> + reg-names = "gmu", "rscc", "gmu_pdc";
>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hfi", "gmu";
>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>> + <&gpucc GPU_CC_CXO_CLK>,
>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> + <&gpucc GPU_CC_AHB_CLK>,
>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>
> This should only be bound to the SMMU
Not sure how this sneaked in. Will remove this.
>
>> + clock-names = "gmu",
>> + "cxo",
>> + "axi",
>> + "memnoc",
>> + "ahb",
>> + "hub",
>> + "smmu_vote";
>> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
>> + <&gpucc GPU_CC_GX_GDSC>;
>> + power-domain-names = "cx",
>> + "gx";
>> + iommus = <&adreno_smmu 5 0xc00>;
>> + operating-points-v2 = <&gmu_opp_table>;
>> +
>> + gmu_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-200000000 {
>> + opp-hz = /bits/ 64 <200000000>;
>
> It looks like this clock only has a 500 Mhz rate
Ack.
-Akhil.
>
> Konrad
