Use new SoC-specific compatible to the SPS SIC in addition to the
"syscon" compatible and rename the node to follow the purpose of it.

Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
---
 arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi 
b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 
522387700fc8ce854c0995636998d2d4237e33df..a106f9f984fcb51dea1fff1515e6f290b36ccf99
 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -402,8 +402,8 @@ saw3_vreg: regulator {
                        };
                };
 
-               sps_sic_non_secure: sps-sic-non-secure@12100000 {
-                       compatible = "syscon";
+               sps_sic_non_secure: interrupt-controller@12100000 {
+                       compatible = "qcom,apq8064-sps-sic", "syscon";
                        reg = <0x12100000 0x10000>;
                };
 

-- 
2.39.5

Reply via email to