On 21/02/2025 11:41, Krzysztof Kozlowski wrote:
> On 20/02/2025 01:50, Jessica Zhang wrote:
>>>
>>> - if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
>>> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
>>> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
>>> if (pll->vco_current_rate < 1557000000ULL)
>>> vco_config_1 = 0x08;
>>> else
>>> @@ -624,6 +648,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy
>>> *phy)
>>> static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
>>> {
>>> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
>>> + void __iomem *base = phy->base;
>>
>> Hi Krzysztof,
>>
>> I see that this line was only previously removed in a patch that was in
>> an older revision of your PHY_CMN_CLK_CFG[01] improvements series
>> ("drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk
>> source").
>>
>> Did you mean for this patch/series to be dependent on that patch? If so,
>> can you make a note of that in the cover letter?
>
> I indeed rebased on top of my previous set, assuming it will get merged
> faster. I will mention this in cover letter.
Ha, not anymore, that "PHY_CMN_CLK_CFG[01]" pieces were already merged
to drm/msm.
Best regards,
Krzysztof
