On Wed, 19 Feb 2025 at 19:04, Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org> wrote: > > On 17/02/2025 20:18, Dmitry Baryshkov wrote: > > On Mon, Feb 17, 2025 at 05:41:36PM +0100, Krzysztof Kozlowski wrote: > >> Implement new features and differences coming in v12.0 of DPU present on > >> Qualcomm SM8750 SoC: > >> 1. 10-bit color alpha. > >> 2. New CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers for pipes and > >> layer mixers. > >> 2. Several differences in LM registers (also changed offsets) for LM > >> crossbar hardware changes. > > > > I'd really prefer for this patch to be split into a logical chunks > > rather than "everything for 12.x" > everything 12.x is still logical chunk. I can split more, but without > guidance what is here logical chunk, will be tricky. > > For example 10-bit color alpha looks like separate feature. But > remaining PIPE/LAYER active - not sure. > > I can split them but I would not call such split necessarily logical.
I'd say, the following items are logical chunks: - ctl->ops.active_fetch_pipes in dpu_encoder_helper_reset_mixers() and dpu_hw_ctl_reset_intf_cfg_v1() (with a proper Fixes tag?) - 10-bit alpha, border color, - active_pipes - blend stage in LM + set_active_lms -- With best wishes Dmitry
