Hi Sean,

Tested-by: Yannick Fertre <yannick.fer...@foss.st.com>

Thanks for this patch,

Yannick

Le 25/11/2024 à 14:49, Sean Nyekjaer a écrit :
When using the DSI interface via DSI2LVDS bridge, it seems a bit harsh
to reguire the requested and the actual px clock to be within
50Hz. A typical LVDS display requires the px clock to be within +-10%.

In case for HDMI .5% tolerance is required.

Signed-off-by: Sean Nyekjaer<s...@geanix.com>
---
  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 +++++-------
  1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 
b20123854c4ad7b3a2cc973a26fc10fd433e8d09..7b32abe0d4f582eea1fbbacad48c84199be3fa23
 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -484,8 +484,6 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int 
lane_mbps,
        return 0;
  }
-#define CLK_TOLERANCE_HZ 50
-
  static enum drm_mode_status
  dw_mipi_dsi_stm_mode_valid(void *priv_data,
                           const struct drm_display_mode *mode,
@@ -525,7 +523,7 @@ dw_mipi_dsi_stm_mode_valid(void *priv_data,
        }
if (!(mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
-               unsigned int px_clock_hz, target_px_clock_hz, lane_mbps;
+               unsigned int px_clock_hz, lane_mbps;
                int dsi_short_packet_size_px, hfp, hsync, hbp, delay_to_lp;
                struct dw_mipi_dsi_dphy_timing dphy_timing;
@@ -533,14 +531,14 @@ dw_mipi_dsi_stm_mode_valid(void *priv_data,
                pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, 
odf);
px_clock_hz = DIV_ROUND_CLOSEST_ULL(1000ULL * pll_out_khz * lanes, bpp);
-               target_px_clock_hz = mode->clock * 1000;
                /*
                 * Filter modes according to the clock value, particularly 
useful for
                 * hdmi modes that require precise pixel clocks.
                 */
-               if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
-                   px_clock_hz > target_px_clock_hz + CLK_TOLERANCE_HZ)
-                       return MODE_CLOCK_RANGE;
+
+               ret = drm_mode_validate_mode(mode, px_clock_hz);
+               if (ret)
+                       return ret;
/* sync packets are codes as DSI short packets (4 bytes) */
                dsi_short_packet_size_px = DIV_ROUND_UP(4 * BITS_PER_BYTE, bpp);

Reply via email to