Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/radeon/r600_dpm.c | 41 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c
b/drivers/gpu/drm/radeon/r600_dpm.c
index 9dda735..b49b0f0 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -989,12 +989,47 @@ int r600_parse_extended_power_table(struct radeon_device
*rdev)
}
}
- /* ppm table */
+ /* ext tables */
if (le16_to_cpu(power_info->pplib.usTableSize) >=
sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER
*)
(mode_info->atom_context->bios + data_offset +
le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset));
+ if ((le16_to_cpu(ext_hdr->usSize) >=
SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) &&
+ ext_hdr->usVCETableOffset) {
+ VCEClockInfoArray *array = (VCEClockInfoArray *)
+ (mode_info->atom_context->bios + data_offset +
+ le16_to_cpu(ext_hdr->usVCETableOffset) + 1);
+ ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =
+ (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
+ (mode_info->atom_context->bios + data_offset +
+ le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
+ 1 + array->ucNumEntries *
sizeof(VCEClockInfo));
+ u32 size = limits->numEntries *
+ sizeof(struct
radeon_vce_clock_voltage_dependency_entry);
+
rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
+ kzalloc(size, GFP_KERNEL);
+ if
(!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
+
kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
+
kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
+
kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
+
kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
+
kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
+ return -ENOMEM;
+ }
+
rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
+ limits->numEntries;
+ for (i = 0; i < limits->numEntries; i++) {
+ VCEClockInfo *vce_clk =
+
&array->entries[limits->entries[i].ucVCEClockInfoIndex];
+
rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
+ le16_to_cpu(vce_clk->usEVClkLow) |
(vce_clk->ucEVClkHigh << 16);
+
rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
+ le16_to_cpu(vce_clk->usECClkLow) |
(vce_clk->ucECClkHigh << 16);
+
rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
+
le16_to_cpu(limits->entries[i].usVoltage);
+ }
+ }
if ((le16_to_cpu(ext_hdr->usSize) >=
SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) &&
ext_hdr->usPPMTableOffset) {
ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *)
@@ -1008,6 +1043,7 @@ int r600_parse_extended_power_table(struct radeon_device
*rdev)
kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
+
kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
return -ENOMEM;
}
rdev->pm.dpm.dyn_state.ppm_table->ppm_design =
ppm->ucPpmDesign;
@@ -1044,6 +1080,7 @@ int r600_parse_extended_power_table(struct radeon_device
*rdev)
kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
kfree(rdev->pm.dpm.dyn_state.ppm_table);
+
kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
return -ENOMEM;
}
if (rev > 0) {
@@ -1096,6 +1133,8 @@ void r600_free_extended_power_table(struct radeon_device
*rdev)
kfree(rdev->pm.dpm.dyn_state.ppm_table);
if (rdev->pm.dpm.dyn_state.cac_tdp_table)
kfree(rdev->pm.dpm.dyn_state.cac_tdp_table);
+ if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
+
kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
}
enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
--
1.8.3.1
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