Uses a different table format if the board supports EVV.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/radeon/r600_dpm.c | 17 +++++++++++++----
drivers/gpu/drm/radeon/radeon.h | 15 +++++++++++----
2 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c
b/drivers/gpu/drm/radeon/r600_dpm.c
index d54a838..ccdf770 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -956,10 +956,19 @@ int r600_parse_extended_power_table(struct radeon_device
*rdev)
return -ENOMEM;
}
for (i = 0; i < cac_table->ucNumEntries; i++) {
-
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
-
le16_to_cpu(cac_table->entries[i].usVddc);
-
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
-
le32_to_cpu(cac_table->entries[i].ulLeakageValue);
+ if (rdev->pm.dpm.platform_caps &
ATOM_PP_PLATFORM_CAP_EVV) {
+
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
+
le16_to_cpu(cac_table->entries[i].usVddc1);
+
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
+
le16_to_cpu(cac_table->entries[i].usVddc2);
+
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
+
le16_to_cpu(cac_table->entries[i].usVddc3);
+ } else {
+
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
+
le16_to_cpu(cac_table->entries[i].usVddc);
+
rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
+
le32_to_cpu(cac_table->entries[i].ulLeakageValue);
+ }
}
rdev->pm.dpm.dyn_state.cac_leakage_table.count =
cac_table->ucNumEntries;
}
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 876f423..e6541e3 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1256,14 +1256,21 @@ struct radeon_clock_voltage_dependency_table {
struct radeon_clock_voltage_dependency_entry *entries;
};
-struct radeon_cac_leakage_entry {
- u16 vddc;
- u32 leakage;
+union radeon_cac_leakage_entry {
+ struct {
+ u16 vddc;
+ u32 leakage;
+ };
+ struct {
+ u16 vddc1;
+ u16 vddc2;
+ u16 vddc3;
+ };
};
struct radeon_cac_leakage_table {
u32 count;
- struct radeon_cac_leakage_entry *entries;
+ union radeon_cac_leakage_entry *entries;
};
struct radeon_phase_shedding_limits_entry {
--
1.8.3.1
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