Hi, it turns out that problem is the read+or of the new value
i reverted my patch and changed reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val; writel_relaxed(reg, mmsys->regs + routes[i].addr); to writel_relaxed(routes[i].val, mmsys->regs + routes[i].addr); and it works too, but maybe it breaks other platforms regards Frank
