>On 12.07.21 19:16, Frank Wunderlich wrote: >> Hi, >> >> it turns out that problem is the read+or of the new value >> >> i reverted my patch and changed >> >> reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val; >> writel_relaxed(reg, mmsys->regs + routes[i].addr); >> >> to >> >> writel_relaxed(routes[i].val, mmsys->regs + routes[i].addr); >> >> and it works too, but maybe it breaks other platforms
A gentle ping. Amy further comments which of both ways is the right one (restoring old output select function or write only without read+or)? regards Frank
