The original modesetting code set MISC to 0x2d, which is <hpgoddev>,
<clksel> and <ioaddsel>
With the conversion to atomic modesetting, <rammapen> accidentally
got enabled as well. Revert this change and initialize MISC with a
constant value of <hgoddev> and <ioaddsel>. The <clksel> bits are set
in mga_crtc_set_plls(), sync flags are set in mgag200_set_mode_regs().
While at it, also rename the flag constant to match the nameing in
the MGA Programming Manual.
Signed-off-by: Thomas Zimmermann <tzimmerm...@suse.de>
Reported-by: kernel test robot <rong.a.c...@intel.com>
Suggested-by: Emil Velikov <emil.l.veli...@gmail.com>
Fixes: db05f8d3dc87 ("drm/mgag200: Split MISC register update into PLL
selection, SYNC and I/O")
Cc: Thomas Zimmermann <tzimmerm...@suse.de>
Cc: Sam Ravnborg <s...@ravnborg.org>
Cc: Emil Velikov <emil.veli...@collabora.com>
Cc: Dave Airlie <airl...@redhat.com>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Gerd Hoffmann <kra...@redhat.com>
Cc: "José Roberto de Souza" <jose.so...@intel.com>
Cc: Andrzej Pietrasiewicz <andrze...@collabora.com>
Cc: Rong Chen <rong.a.c...@intel.com>
Cc: John Donnelly <john.p.donne...@oracle.com>
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 6 ++----
drivers/gpu/drm/mgag200/mgag200_reg.h | 2 +-
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c
b/drivers/gpu/drm/mgag200/mgag200_mode.c
index f16bd278ab7e4..3b7235bd0bcba 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1018,10 +1018,8 @@ static void mgag200_init_regs(struct mga_device *mdev)
if (mdev->type == G200_EW3)
WREG_ECRT(0x34, 0x5);
- misc = RREG8(MGA_MISC_IN);
- misc |= MGAREG_MISC_IOADSEL |
- MGAREG_MISC_RAMMAPEN |
- MGAREG_MISC_HIGH_PG_SEL;
+ misc = MGAREG_MISC_HPGODDEV |
+ MGAREG_MISC_IOADSEL;
WREG8(MGA_MISC_OUT, misc);
}
diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h
b/drivers/gpu/drm/mgag200/mgag200_reg.h
index 29f7194faadc0..f6629e0d4bdf2 100644
--- a/drivers/gpu/drm/mgag200/mgag200_reg.h
+++ b/drivers/gpu/drm/mgag200/mgag200_reg.h
@@ -228,7 +228,7 @@
#define MGAREG_MISC_CLK_SEL_MGA_PIX (0x2 << 2)
#define MGAREG_MISC_CLK_SEL_MGA_MSK (0x3 << 2)
#define MGAREG_MISC_VIDEO_DIS (0x1 << 4)
-#define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5)
+#define MGAREG_MISC_HPGODDEV BIT(5)
#define MGAREG_MISC_HSYNCPOL BIT(6)
#define MGAREG_MISC_VSYNCPOL BIT(7)
--
2.27.0
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