Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
---
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 4 ++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 21 +++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
index 22b4bce6431f..bc3d5219e5b4 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
@@ -84,6 +84,10 @@
clocks = <&dpdma_clk>;
};
+&dpsub {
+ clocks = <&dp_aclk>, <&dp_aud_clk>, <&drm_clock>;
+};
+
&fpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 766389ddf97f..35d310337afe 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -407,6 +407,27 @@
interrupts = <0 112 4>;
};
+ dpsub: display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&dpdma 0>,
+ <&dpdma 1>,
+ <&dpdma 2>,
+ <&dpdma 3>;
+ };
+
gem0: ethernet@ff0b0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";
--
Regards,
Laurent Pinchart
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