[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

Tue, 22 Nov 2016 21:12:34 +0000 

https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #4 from Arek Ruśniak <arek.rusi at gmail.com> ---
Created attachment 128153
  --> https://bugs.freedesktop.org/attachment.cgi?id=128153&action=edit
dmesg - revert refine uvd 6.0 clock gate feature

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