From: Marek Olšák <marek.ol...@amd.com>
This reverts commit 31b4dfe24e903e995a32f17e9a9cafbbecabc77a.
See the comment in the code. Basically, don't do cleanups in this header.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
---
include/uapi/drm/radeon_drm.h | 133 ++++++++++++++++++++++--------------------
1 file changed, 69 insertions(+), 64 deletions(-)
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 490a59c..6b019f1 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -30,6 +30,11 @@
* Keith Whitwell <keith at tungstengraphics.com>
*/
+/* IT IS NOT ALLOWED TO CHANGE THIS HEADER WITHOUT DOING THE SAME IN LIBDRM !!!
+ * THIS IS NOT A UAPI HEADER. IT IS ONLY A MIRROR OF ITS COUNTERPART IN LIBDRM.
+ * USERSPACE SHOULD USE THE HEADERS FROM LIBDRM. NOT THIS ONE.
+ */
+
#ifndef __RADEON_DRM_H__
#define __RADEON_DRM_H__
@@ -797,9 +802,9 @@ typedef struct drm_radeon_surface_free {
#define RADEON_GEM_DOMAIN_VRAM 0x4
struct drm_radeon_gem_info {
- __u64 gart_size;
- __u64 vram_size;
- __u64 vram_visible;
+ uint64_t gart_size;
+ uint64_t vram_size;
+ uint64_t vram_visible;
};
#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
@@ -811,11 +816,11 @@ struct drm_radeon_gem_info {
#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create {
- __u64 size;
- __u64 alignment;
- __u32 handle;
- __u32 initial_domain;
- __u32 flags;
+ uint64_t size;
+ uint64_t alignment;
+ uint32_t handle;
+ uint32_t initial_domain;
+ uint32_t flags;
};
/*
@@ -829,10 +834,10 @@ struct drm_radeon_gem_create {
#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
struct drm_radeon_gem_userptr {
- __u64 addr;
- __u64 size;
- __u32 flags;
- __u32 handle;
+ uint64_t addr;
+ uint64_t size;
+ uint32_t flags;
+ uint32_t handle;
};
#define RADEON_TILING_MACRO 0x1
@@ -854,72 +859,72 @@ struct drm_radeon_gem_userptr {
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
struct drm_radeon_gem_set_tiling {
- __u32 handle;
- __u32 tiling_flags;
- __u32 pitch;
+ uint32_t handle;
+ uint32_t tiling_flags;
+ uint32_t pitch;
};
struct drm_radeon_gem_get_tiling {
- __u32 handle;
- __u32 tiling_flags;
- __u32 pitch;
+ uint32_t handle;
+ uint32_t tiling_flags;
+ uint32_t pitch;
};
struct drm_radeon_gem_mmap {
- __u32 handle;
- __u32 pad;
- __u64 offset;
- __u64 size;
- __u64 addr_ptr;
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t offset;
+ uint64_t size;
+ uint64_t addr_ptr;
};
struct drm_radeon_gem_set_domain {
- __u32 handle;
- __u32 read_domains;
- __u32 write_domain;
+ uint32_t handle;
+ uint32_t read_domains;
+ uint32_t write_domain;
};
struct drm_radeon_gem_wait_idle {
- __u32 handle;
- __u32 pad;
+ uint32_t handle;
+ uint32_t pad;
};
struct drm_radeon_gem_busy {
- __u32 handle;
- __u32 domain;
+ uint32_t handle;
+ uint32_t domain;
};
struct drm_radeon_gem_pread {
/** Handle for the object being read. */
- __u32 handle;
- __u32 pad;
+ uint32_t handle;
+ uint32_t pad;
/** Offset into the object to read from */
- __u64 offset;
+ uint64_t offset;
/** Length of data to read */
- __u64 size;
+ uint64_t size;
/** Pointer to write the data into. */
/* void *, but pointers are not 32/64 compatible */
- __u64 data_ptr;
+ uint64_t data_ptr;
};
struct drm_radeon_gem_pwrite {
/** Handle for the object being written to. */
- __u32 handle;
- __u32 pad;
+ uint32_t handle;
+ uint32_t pad;
/** Offset into the object to write to */
- __u64 offset;
+ uint64_t offset;
/** Length of data to write */
- __u64 size;
+ uint64_t size;
/** Pointer to read the data from. */
/* void *, but pointers are not 32/64 compatible */
- __u64 data_ptr;
+ uint64_t data_ptr;
};
/* Sets or returns a value associated with a buffer. */
struct drm_radeon_gem_op {
- __u32 handle; /* buffer */
- __u32 op; /* RADEON_GEM_OP_* */
- __u64 value; /* input or return value */
+ uint32_t handle; /* buffer */
+ uint32_t op; /* RADEON_GEM_OP_* */
+ uint64_t value; /* input or return value */
};
#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
@@ -939,11 +944,11 @@ struct drm_radeon_gem_op {
#define RADEON_VM_PAGE_SNOOPED (1 << 4)
struct drm_radeon_gem_va {
- __u32 handle;
- __u32 operation;
- __u32 vm_id;
- __u32 flags;
- __u64 offset;
+ uint32_t handle;
+ uint32_t operation;
+ uint32_t vm_id;
+ uint32_t flags;
+ uint64_t offset;
};
#define RADEON_CHUNK_ID_RELOCS 0x01
@@ -965,29 +970,29 @@ struct drm_radeon_gem_va {
/* 0 = normal, + = higher priority, - = lower priority */
struct drm_radeon_cs_chunk {
- __u32 chunk_id;
- __u32 length_dw;
- __u64 chunk_data;
+ uint32_t chunk_id;
+ uint32_t length_dw;
+ uint64_t chunk_data;
};
/* drm_radeon_cs_reloc.flags */
#define RADEON_RELOC_PRIO_MASK (0xf << 0)
struct drm_radeon_cs_reloc {
- __u32 handle;
- __u32 read_domains;
- __u32 write_domain;
- __u32 flags;
+ uint32_t handle;
+ uint32_t read_domains;
+ uint32_t write_domain;
+ uint32_t flags;
};
struct drm_radeon_cs {
- __u32 num_chunks;
- __u32 cs_id;
- /* this points to __u64 * which point to cs chunks */
- __u64 chunks;
+ uint32_t num_chunks;
+ uint32_t cs_id;
+ /* this points to uint64_t * which point to cs chunks */
+ uint64_t chunks;
/* updates to the limits after this CS ioctl */
- __u64 gart_limit;
- __u64 vram_limit;
+ uint64_t gart_limit;
+ uint64_t vram_limit;
};
#define RADEON_INFO_DEVICE_ID 0x00
@@ -1046,9 +1051,9 @@ struct drm_radeon_cs {
#define RADEON_INFO_GPU_RESET_COUNTER 0x26
struct drm_radeon_info {
- __u32 request;
- __u32 pad;
- __u64 value;
+ uint32_t request;
+ uint32_t pad;
+ uint64_t value;
};
/* Those correspond to the tile index to use, this is to explicitly state
--
2.7.4
