Hi,

> of the drift remains a mistery (probably due to the implementation of the PLL,
> but I cannot understand why Phase Locked Loops would drift in Phase !).

If the phase comparator is digital ( i.e. a XOR ) and the input clock
is somewhat analog, the gate thresholds might vary depending on
temperature, thus shifting the cycle a bit.

Just a thought.

Cheers,

    Sylvain

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