Hi Vince,

Changing a little the topic, have you managed to run your SoftDVB code to
work on multiple USRPs in order to create a SFN DVB configuration?

Best regards,
Rafael Diniz

> Josh,
> I agree this would be a great feature.
>
> vince
>
>
>>
>> There is a clock sync pin (cgen_sync_b in the fpga top level).
>> Presumably, a shared PPS could trigger the clock sync signal across
>> multiple B100. This would synchronously reset the phase across all N
>> devices. It would require a little FPGA work.
>>
>> -Josh
>>



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